Semiconductor device

ABSTRACT

In the case where a first semiconductor chip and a second semiconductor chip are stacked, both the semiconductor chips are connected using micro bumps, such that a circuit block in the first semiconductor chip and a circuit block in the second semiconductor chip are connected by the micro bumps, and the circuit block in the second semiconductor chip is also connected to the external electrode by the micro bumps through the first semiconductor chip. Further, the micro bumps that connect circuit blocks of both the semiconductor chips and the micro bumps that connect the circuit block in one chip to an external electrode are arranged in different positions.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Division of and claims the benefit of priorityunder 35 U.S.C §120 from U.S. Ser. No. 10/553,466, filed Oct. 17, 2005,which is the National Stage of International Application No.PCT/JP05/02196 and claims the benefit of priority under 35 U.S.C §119from Japanese Patent Application No. 2004-038403, filed on Feb. 16,2004, the entire contents of each of which are incorporated herein byreference.

TECHNICAL FIELD

The present invention relates to a semiconductor device formed of aplurality of semiconductor chips stacked.

BACKGROUND ART

The SIP (System in package) technology with which a plurality ofsemiconductor chips are stacked in three dimensional directions (in thedirection of height) to be integrated in one package has been developed.FIGS. 5 and 6 are drawings showing an example of a structure of suchsemiconductor device of prior art. FIG. 5 shows a cross sectional viewand FIG. 6 shows a plan view seen from the above. In this example, asecond chip 20 is stacked on a first chip 10, and a memory (DRAM) 11 andothers are included in the first chip 10 as an integrated circuit and aCPU (Central Processing Unit) Block 21 and others are included in thesecond chip 20 as an integrated circuit. Further, the first chip 10 ismade to be somewhat larger than the second chip 20.

The memory 11 in the first chip 10 is formed of a plurality of DRAMs; aselector 12 is provided to select from the plurality of DRAMs; and thememory 11 is connected to the CPU block 21 on the second chip 20 sidethrough the selector 12. A selector is also provided on the CPU block 21side. The details with respect to the structure connected through theseselectors are described later; each selector also has a registerfunction that retains data temporarily.

As the structure for connecting the memory 11 and the CPU block 21, asshown in FIG. 6, a pad 13 a connected to the selector 12 with theinternal wiring is provided on the first chip 10 side and a pad 22 aconnected to the CPU block 21 with the internal wiring is provided onthe second chip 20 side. Then, the pad 13 a on the first chip 10 sideand the pad 22 a on the second chip 20 side are connected with a wire 31such as a copper wire. Although only one set of the pads 13 a, 22 a andwire 31 is shown in FIG. 6 to make the explanation simplified, aplurality of those sets are arranged in actuality, in which paralleldata can be transferred.

A predetermined number of pads 22 b connected to the CPU block 21 withthe internal wiring are provided on the second chip 20 side in order toconnect the CPU block 21 to the outside. A predetermined number of pads13 b are provided on the first chip 10 side at a position adjacent toeach of pads 22 b, and further a predetermined number of pads 13 cconnected to the pad 13 b with the internal wiring are provided in theperipheral portion of the first chip 10. Then, the pads 22 b on thesecond chip 20 side and the pads 13 b on the first chip 10 side areconnected with the wire 31, and the pads 13 c in the peripheral portionof the first chip 10 are connected to the electrode on the package side(not shown in the figure) with the wire 32.

Hereupon, FIG. 7 shows an example of a state of prior art in which theCPU block 21 on the second chip 20 side and the memory 11 on the firstchip 10 side are connected. In the example of FIG. 7, four DRAMs 11 a,11 b, 11 c and lid constitute the memory 11, and each of DRAMs 11 a to11 d is connected to the register and selector 12 through the internalwiring in the chip 10. The selector 12 is connected to the register andselector 21 a on the CPU block 21 side through the wire 31 connectingthe chip 10 and chip 20, and the register and selector 21 a is connectedto the circuit in the CPU block 21 through the internal wiring.

As shown in FIG. 7, the CPU block 21 side and the DRAMs 11 a to 11 dside are connected through the registers and selectors 12, 21 a, toperform selectively the readout from or writing to the four DRAMs 11 ato 11 d, and further the readout or writing is performed dividedly inone selected DRAM. For example, in the case where data of originally 128bits is read or written in parallel in one DRAM, both the selectors 12and 21 a are connected with thirty-two wires, and the readout or writingof 128 bits data is performed four times dividedly.

The above described structure in which a plurality of semiconductorchips are stacked is disclosed in Published Japanese Patent ApplicationNo. H8-167703 issued by Japanese Patent Office.

Here, in the structure shown in FIGS. 5 through 7, the CPU block on thefirst chip 10 and the memory on the second chip 20 are connected throughthe register and selector, so that the number of the wires 31 (and padsconnected to the wires) connecting both the chips 10, 20 is made to becomparatively small and consequently wires connecting two chipcomponents are reduced. If the number of wires increases, it takes timeto connect chip components, which is unfavorable. Further, because thereis a limit regarding the area on the chip where pads can physically bearranged, the number that can be connected is also restricted.

However, when the writing and readout are dividedly performed with theconnection through the selector as described above, there is a problemthat it takes time to access the memory. Although it is necessary toincrease the transfer rate of data in order to shorten the time requiredfor the access, there are such problems that the distortion is easilycaused with respect to the waveform at the high transfer rate due to alarge inductance component of the wire portion in the case where theconnection was made with the wires and that the undesirable radiationand the power consumption may increase.

Further, in the case where two chips are stacked and connected asdescribed above, only in order to connect the circuit block in one chipto an electrode on the package side, the chip is required to beconnected to the other chip component with the wire, and so there is aproblem that the connected structure becomes complicated. Specifically,for example, in the example of FIGS. 5 and 6, in order to connect theCPU block 21 on the second chip 20 side to the electrode on the packageside, the connection is made to the internal wiring on the first chip 10side with the pad 22 b, wire 31 and pad 13 b, and further the connectionis made from the pad 13 c in the peripheral portion of the first chip 10to the electrode on the package side with the wire, and so the connectedstructure becomes complicated. Further, when the wire (part of the wire31) to connect the CPU block 21 and the electrode on the package sideand the wire (part of the wire 31) to connect the CPU block 21 and thememory are arranged adjacently to each other, the influence of the abovedescribed undesired radiation is mutually received, which is notpreferable in view of characteristics thereof.

The present invention is to provide a semiconductor device in which theconnected structure can be simplified and favorable characteristics canbe obtained in the case of stacking a plurality of semiconductor chips.

DISCLOSURE OF THE INVENTION

The first aspect of the present invention is a semiconductor deviceincluding a first semiconductor chip and a second semiconductor chipstacked, wherein the first semiconductor chip includes a first electrodeportion for connecting to the external electrode with wire, a secondelectrode portion having micro bumps for connecting a circuit in thesecond semiconductor chip to the first electrode portion, and a thirdelectrode portion having micro bumps for connecting a circuit block inthe first semiconductor chip to the circuit in the second semiconductorchip; and the second semiconductor chip includes a fourth electrodeportion having micro bumps for connecting to the second electrodeportion in the first semiconductor chip, and a fifth electrode portionhaving micro bumps for connecting to the third electrode portion in thefirst semiconductor chip.

The second aspect of the present invention is the semiconductor deviceaccording to the first aspect of the invention, wherein the secondelectrode portion in the first semiconductor chip and the fourthelectrode portion in the second semiconductor chip are arranged in thevicinity of a peripheral portion on each chip, and the third electrodeportion in the first semiconductor chip and the fifth electrode portionin the second semiconductor chip are arranged in the vicinity of thecenter portion on each chip.

The third aspect of the present invention is the semiconductor deviceaccording to the first aspect of the present invention, wherein thefirst semiconductor chip includes a circuit block of a memory, and thesecond semiconductor chip includes a circuit block of a control portion.

The fourth aspect of the present invention is the semiconductor deviceaccording to the first aspect of the present invention, wherein themicro bumps constituting the third and fifth electrode portions arearranged at least by the number corresponding to the number of bits of amemory which is included in the first semiconductor chip and in whichthe readout or writing is performed in parallel.

According to the present invention having the above structure, since twosemiconductor chips are connected using micro bumps, the twosemiconductor chips can be connected easily with a number of terminals.Therefore, in the case where, for example, the circuit block of a memoryis provided in the first semiconductor chip and the circuit block of acontrol portion is provided in the second semiconductor chip and thecontrol portion and the memory are connected, the both chips can beconnected by a necessary number of bits for performing the writing toand readout from the memory and the structure can be simplified withoutproviding the selector and others to select the memory.

Further, since the electrode portion where the circuit block in thefirst semiconductor chip and the circuit block in the secondsemiconductor chip are connected by the micro bumps and the electrodeportion where the other micro bumps than those are used for connectionare arranged in the different positions on the chip, it becomes possibleto make an arrangement in which the data transfer between the circuitblocks in the two semiconductor chips and the data transfer to theoutside of the semiconductor device are performed without interference,and the semiconductor device having favorable characteristics can beobtained.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a sectional view showing an example of a structure of thevertical section according to an embodiment of the present invention;

FIG. 2 is a perspective view showing an example of a state beforejoining according to an embodiment of the present invention;

FIG. 3 is a perspective view showing a second chip in the state upsidedown from FIGS. 1 and 2 according to an embodiment of the presentinvention;

FIG. 4 is a block diagram showing an example of a connection of circuitblocks in a device according to an embodiment of the present invention;

FIG. 5 is a sectional view showing an example of a structure of thevertical section according to prior art;

FIG. 6 is a plan view showing an example of a semiconductor deviceaccording to prior art; and

FIG. 7 is a block diagram showing an example of a connection between theblocks in a semiconductor device of prior art.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention is explainedreferring to FIGS. 1 to 4.

FIGS. 1 and 2 are diagrams showing a structure of a semiconductor deviceof this embodiment in the state before joining two chips 100 and 200,and FIG. 1 shows a sectional view and FIG. 2 shows a perspective view.Further, FIG. 3 shows the chip 100 upside down from FIG. 2.

In this embodiment, the second chip 200 is stacked on the first chip100; DRAMs 111, 112 113 and 114 of memories and others are included inthe first chip 100 as the integrated circuit; and a CPU (CentralProcessing Unit) block 210 and others are included in the second chip200 as the integrated circuit. Further, the first chip 100 is madesomewhat larger in size than that of the second chip 200. The four DRAMs111 to 114 in the first chip 100 are directly connected to the CPU block210 on the second chip 200 side through the electrodes having a microbump 121, 221.

A number of electrodes having a micro bump 121 that connect the fourDRAMs 111, 112, 113 and 114 in the first chip 100 to the CPU block 210on the second chip 200 side, as shown in FIG. 2, are arranged almost inthe center of the first chip 100 in the matrix shape with a specificpitch.

Further, as shown in FIG. 3, in the center of the second chip 200 areprovided the electrodes having a micro bump 221 formed of similar sizedconvexity of a conductive member of the same number and of the samearrangement as the electrodes 121 in the matrix shape on the first chip100 side. With respect to the electrodes 121 and 221, one electrode hasa bump formed of a convexity of a conductive member of 30 μm in diameterfor example, and is plated with SnAg or the like. The other electrodeshaving a micro bump 122, 222 described later on have the similarstructures.

Further, when the second chip 200 is stacked on the first chip 100, theelectrodes having a micro bump 121 on the first chip 100 side and theelectrodes having a micro bump 221 on the second chip 200 side areprecisely positioned to be contacted and then fixing processing such asheating is performed, and consequently the micro bumps mutuallycontacted are fixed in the state electrically conductive. By fixing inthis way, as shown in FIG. 1 for example, the DRAM 111 in the first chip100 is connected to the CPU block 210 through the internal wiring 101,the electrodes having a micro bump 121, 221 and the internal wiring 201.The DRAM 112 in the first chip 100 is connected to the CPU block 210through the internal wiring 102, the electrodes having a micro bump 121,221 and the internal wiring 202. The DRAM 113 in the first chip 100 isconnected to the CPU block 210 through the internal wiring 103, theelectrodes having a micro bump 121, 221 and the internal wiring 203. TheDRAM 114 in the first chip 100 is connected to the CPU block 210 throughthe internal wiring 104, the electrodes having a micro bump 121, 221 andthe internal wiring 204.

In this embodiment, the input bus and output bus for the CPU block 210and each of DRAMs 111, 112, 113, 114 are individually prepared in thenecessary bit width for each DRAM. For example, assuming that the bitwidth of the bus is 128 bits, 256 bits width in total, namely 128 bitseach, is necessary for the input bus and output bus per DRAM, andfurthermore, the bus width of 256×4=1024 bits is necessary, because fourDRAMs are arranged. Therefore, at least 1024 pieces of the electrodeshaving a micro bump 121 on the first chip 100 side and at least 1024pieces of the electrodes having a micro bump 221 on the second chip 200side are arranged respectively. In actuality, since lines for exchangingcontrol data and the like are also needed, more number of electrodeshaving a micro bump 121, 221 are arranged.

Further, the CPU block 210 in the second chip 200 is connected throughthe wire 301 attached to the first chip 100 to the electrode attached tothe package (not shown in the figure) which houses the chips 100 and200, and for this connection, the electrode having a micro bump 222connected to the CPU block 210 through the internal wiring 205 (refer toFIG. 1) is prepared, for example. This electrode having a micro bump222, is arranged in the peripheral portion of the second chip 200, asshown in FIG. 3. With respect to this electrode having a micro bump 222,several hundred or more thereof are provided.

Further, the same number of electrodes having a micro bump 122 as theelectrodes having a micro bump 222 is arranged at the position on thefirst chip 100 side that faces the electrodes having a micro bump 222.The electrodes having a micro bump 222 are individually connected to aplurality of pads 131 formed of a conductive member arranged in theperipheral portion on the first chip 100 through the internal wiring 105(refer to FIG. 1) in the first chip 100. As shown in FIGS. 1 and 2, eachof the pads 131 is connected by wire bonding to an electrode (not shownin the figure) on the package side through the individual wire 301,respectively.

At the time when connecting the first chip 100 and the second chip 200as described above, the electrodes having a micro bump 122, 222 in theperipheral portions on both the chips 100 and 200 are also connectedsimultaneously.

FIG. 4 is a block diagram of this embodiment showing the state in whichcircuits are connected between each of DRAMs 111 to 114 in the firstchip 100 and the CPU block 210 in the second chip 200. In thisembodiment, as explained above, the necessary input bus and output bus(128 bits width respectively, for example) of each of DRAMs 111 to 114are individually connected to the CPU 211. Therefore, the register andselector needed in the example of prior art shown in FIG. 7 are notnecessary, and the CPU 210 can be accessed directly from each of DRAMs111 to 114.

Further, the CPU block 210 includes an SRAM 212, a data input/outputinterface 213, an analogue/digital converter 214 and so on, other thanthe CPU of the control portion, and signal wires such as a bus connectedto these circuits in the CPU block 210 are connected to the electrodeson the package side with the necessary bit number through the electrodeshaving a micro bump 122, 222, the pads 131 and the wires 301.

According to the semiconductor device having the above explainedstructure of this embodiment, since a plurality of memory elements 111to 114 in the first chip 100 and the CPU block 210 in the second chipare directly connected by the bit width required for each memory as theinput bus and/or the output bus and the connection is not made throughthe register and selector, the structure for control is simplified andnecessary data can be input and/or output directly and therefore theexchange of data between two chips can be performed fast at acomparatively low transfer rate. Further, the power consumption may besuppressed low, because there is no need to make the transfer rate highand no need to provide the selector and the like.

Further, since the electrodes having a micro bump 121, 221 to performthe input/output of data between the memory elements 111 to 114 and theCPU block 210 are arranged in almost the center on each of the chips 100and 200, and the electrodes having a micro bump 122, 222 to connect theCPU block 210 to the electrodes attached to the package are arranged inthe peripheral portion distantly (arranged at different position), theinterference between the data exchanged between the CPU block 210 andthe memory elements 111 to 114 and the data exchanged between the CPUblock 210 and the outside of the package can be prevented and theelectrical characteristics as the semiconductor device can be madeexcellent.

Note that, in the above mentioned embodiment, the DRAM is arranged onthe first chip side and the CPU block is arranged on the second chipside, however, these circuit blocks may be each provided in oppositechips. Further, on each chip may be arranged other circuit blocks thanthe CPU block of the control portion and the DRAM of the memory element,and the circuit blocks between both chips may be connected directlythrough the micro bumps.

1. A semiconductor device comprising: a first semiconductor chipincluding a plurality of memory elements and a second semiconductor chipincluding a central processing unit (CPU) block stacked, wherein saidfirst semiconductor chip includes a first electrode portion forconnecting to an external electrode through wiring, a second electrodeportion having micro bumps for connecting said CPU block in said secondsemiconductor chip to said first electrode portion, and a thirdelectrode portion having micro bumps for providing a data connectionfrom said memory block in said first semiconductor chip to said CPUblock in said second semiconductor chip; and said second semiconductorchip includes a fourth electrode portion having micro bumps forconnecting to the second electrode portion in said first semiconductorchip, and a fifth electrode portion having micro bumps for connecting tothe third electrode portion in said first semiconductor chip, whereinthe second electrode portion in said first semiconductor chip and thefourth electrode portion in said second semiconductor chip are arrangedin a vicinity of a peripheral portion on each chip and the thirdelectrode portion in said first semiconductor chip and the fifthelectrode portion in said second semiconductor chip are arranged in avicinity of a center portion on each chip, and a selector is provided onthe second semiconductor chip containing the CPU block, said selectorselects from one memory element from among the plurality of memoryelements on the first semiconductor chip, and said selector contains aregister to temporarily store data.
 2. A semiconductor devicecomprising: a first semiconductor chip including a plurality of memoryelements, a second semiconductor chip including a central processingunit (CPU) block stacked, a first electrode configured to connect thefirst semiconductor chip to an external electrode through wiring, asecond electrode having micro bumps configured to connect said CPU blockin said second semiconductor chip to the first electrode, a thirdelectrode having micro bumps configured to provide a data connectionfrom said memory block in said first semiconductor chip to said CPUblock in said second semiconductor chip, a fourth electrode having microbumps configured to connect to the second electrode in said firstsemiconductor chip, and a fifth electrode having micro bumps configuredto connect to the third electrode in said first semiconductor chip,wherein the second electrode in said first semiconductor chip and thefourth electrode in said second semiconductor chip are located in avicinity of a peripheral portion on each chip, and the third electrodein said first semiconductor chip and the fifth electrode in said secondsemiconductor chip are located in a vicinity of a center portion on eachchip, and wherein a selector on the second semiconductor chip containingthe CPU block is configured to select one memory element from among theplurality of memory elements on the first semiconductor chip and isconfigured to contain a register to temporarily store data.